1. Field of the Invention
The present invention relates to the field of pseudo static random access memory and, more particularly, to an embedded auto-refresh circuit to refresh static random access memory cells without the associated processing system being halted.
2. Description of Related Art
Conventionally, the Static Random Access Memory (SRAM) cell is typically configured to a Six-Transistor SRAM cell, as shown in FIG. 6, or a Resistive-Load SRAM cell, as shown in FIG. 7. In addition, FIG. 8 shows a Four-Transistor pseudo SRAM cell, which is able to save about half the layout area as compared to the Six-Transistor SRAM, and does not need an additional process to form a resistor as compared to the Resistive-Load SRAM. Furthermore, the Four-Transistor pseudo SRAM cell is provided with a better data stability as compared to the Dynamic Random Access Memory (DRAM). Therefore, the above Four-Transistor pseudo SRAM cells are widely used in electronic circuitry. However, it is known that the electric charge in the drain of such a Four-Transistor pseudo SRAM cell is prone to disappear due to sub-threshold leakage. As such, it is necessary to refresh the Four-Transistor pseudo SRAM cells in every predefined period of time in order to ensure the integrity of data.
A memory circuit constituted by the above Four-Transistor pseudo SRAM cell is shown in FIG. 9. As shown, there are a plurality of cells 91 arranged in a matrix form. The cells 91 of each row are connected to a word line (WL) 92, while the cells 91 of each column are connected to a bit line pair consisting of a bit line (BL) 931 and an inverted bit line (BL) 932. To access memory, a pre-charge circuit 95 is enabled to charge the bit line 931 and inverted bit line 932 to a voltage level of logic "1" to clear the original data on the bit line pair, so as to avoid data overwriting in the subsequent memory access. The address from an address bus 96 is decoded by an address decoder 94 to select the cells 91 on a word line 92 to perform a read or write operation.
A block diagram of a typical system configured by the above Four-Transistor pseudo SRAM and the timing diagram thereof are shown in FIG. 10 and FIG. 11, respectively. As shown in FIG. 10, an additional refresh circuit 97 is employed to carry out the memory refresh operation. That is, when the memory system 98 is required to be refreshed, the refresh circuit 97 stops the current procedure in the processing system 99 and asserts the R/W signal to issue a pseudo read operation to the memory system 98 for memory refresh. It is obvious that the processing system 99 has to be halted when the memory system 98 is in refresh, and thus a lot of bandwidth that can be used for data processing is wasted. The drawback of wasting bandwidth is even more troublesome as the semiconductor manufacturing process develops into the deep sub-micron technique, hence the sub-threshold leakage is increasing. Therefore, there is a need for the above Four-Transistor pseudo SRAM to be improved.